High-speed operations have been required of a large scale integrated circuit. Reduction of a parasitic capacitance is indispensable for higher-speed operations of the large scale integrated circuit. An SOI (Silicon on Insulator) substrate technique has been expected as a promising technique for reducing this parasitic capacitance. FIG. 11A is a schematic diagram of a semiconductor device 90 (hereinafter referred to as “SOI device 90”) where a transistor and the like are formed in an SOI substrate. FIG. 11B is a schematic diagram of a semiconductor device 100 (hereinafter referred to as “Si substrate device 100”) where a transistor and the like are formed in an Si substrate. As shown in FIG. 11A, the SOI substrate is constituted of an Si-made active layer substrate (SOI layer) 91, a support substrate 92 supporting the SOI layer 91 from the rear side, and a buried oxide film (SiO2) 93 having the thickness of several μm and formed between the two substrates. A device 101 such as a transistor is formed in the active layer substrate 91 of the SOI substrate to thereby complete the SOI device 90. The SOI device 90 is separated into the SOI layer 91 and the support substrate 92 across the buried oxide film 93. Therefore, a transistor or the like can be formed in the thin SOI layer 91 in the SOI device 90, and a parasitic capacitance of source/drain regions can be reduced to thereby enable higher-speed operations than the Si substrate device 100 of the related art, in which a transistor or the like is directly formed in the Si substrate 94 as shown in FIG. 11B.
However, the SOI device 90 has a problem that defects are likely to occur in a gate oxide film of the device due to metal impurities generated in production facility or the like at the time of manufacturing a device. As shown in FIG. 11B, the Si substrate device 100 of the related art includes gettering sites enough to trap metal impurities 95, in the Si substrate 94. The gettering sites trap the metal impurities 95 or the like. Thus, even if metal impurities are mixed in the Si substrate 94 during a manufacturing process of the Si substrate device 100, the gettering sites trap the metal impurities 95 or the like. As a result, defects of the gate oxide film 96 in the device due to the metal impurities 95 or the like can be suppressed.
On the other hand, in the SOI device 90 of FIG. 11A, the SOI layer 91 is thin, so the number of gettering sites that trap the metal impurities 95 is small. Further, SiO2 for forming the buried oxide film 93 is interposed between the Si-made SOI layer 91 and the support substrate 92. Since a diffusion coefficient of metal is lower in SiO2 than in Si, the metal impurities 95 cannot pass through the SiO2 with ease. As a result, the metal impurities 95 are accumulated in the SOI layer 91. That is, the metal impurities 95 are accumulated in the SOI layer 91, with the result that the metal impurities 95 are more likely to adversely affect a device formed in the SOI layer substrate 91. The contamination with the metal impurities 95 might cause junction leak or reduction in breakdown voltage of a gate oxide film.
As a method of suppressing defects of the gate oxide film due to metal impurities, there is a gettering technique forming a crystal defect in a substrate and capturing metal impurities with the crystal defect. The gettering technique is disclosed in Patent Document 1. Referring to FIGS. 12A to 12H, a manufacturing method of an SOI device with gettering sites as disclosed in Patent Document 1 is described. As shown in FIG. 12A, a support substrate 92 is first prepared. As shown in FIG. 12B, a buried oxide film 93 is then formed to surround the support substrate 92.
As shown in FIG. 12C, an active layer substrate 91 is prepared, and a predetermined amount of dopant such as arsenic or antimony or the like is selectively doped to the active layer substrate 91. At this time, the surface portion of the Si-made active layer substrate 91 is turned amorphous through the dopant injection to form an amorphous layer 98. As shown in FIG. 12D, the active layer substrate 91 is subjected to heat treatment next to diffuse the dopant. At this time, the amorphous layer 98 is recrystallized. Here, the heat treatment for diffusing the dopant is carried out under an oxygen atmosphere, so oxygen, silicon, and the like are supplied to the amorphous layer 98 to hinder the amorphous layer 98 from recrystallizing, and crystal defects 97 are formed. At this time, a silicon oxide film 99 is formed around the active layer substrate 91. After that, as shown in FIG. 12E, the active layer substrate 91 is treated with SC1 cleaning and SC2 cleaning prior to bonding for the purpose of removing contaminants. As shown in FIG. 12F, the support substrate 92 with the buried oxide film 93 is then bonded to the active layer substrate 91 on the crystal defect 97 side, followed by heat treatment. As shown in FIG. 12G, the active layer substrate 91 is ground or polished. As shown in FIG. 12H, a device 101 such as a transistor or the like is formed in the ground or polished surface of the active layer substrate 91 to thereby complete an SOI device.
[Patent Document 1]
    Japanese Unexamined Patent Application Publication No. 2006-5341